Masking Memory Access Latency with a Compiler-Assisted Data Prefetch Controller A THESIS SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL OF THE UNIVERSITY OF MINNESOTA BY

and have found that it is complete and satisfactory in all respects, and that any and all revisions required by the final examining committee have been made ABSTRACT Scientific and other data-intensive applications often generate memory referencing patterns that exhibit little data reuse, resulting in poor cache utilization and run-times that can be dominated by memory delays. Data prefetching attempts to mask these delays by fetching data into the processor cache hierarchy in advance of the data's actual use. In this thesis, a data prefetch controller (DPC) is proposed that combines the low instruction overhead of hardware prefetching techniques with the accuracy of software prefetching. The DPC issues prefetch requests on behalf of the processor by executing an independent program that is derived from analysis of the application source code. This compile-time information allows the DPC to replicate portions of the processor's data referencing pattern at run-time. The prefetch controller anticipates upcoming processor data references through a combination of explicit processor commands and address bus snooping hardware that detects when previously prefetched data have been referenced by the processor. The efficacy of the prefetch controller in reducing program run-times is established through software simulation of the DPC, processor and memory hierarchy. These simulations are driven by executable files produced by a commercial compiler. The source files for both the processor program and the DPC program are generated from the original application source code by a custom source-to-source transformer. Simulation results show that the DPC improved the execution times of a subset of the SPECfp95 benchmark suite by 41% to 64%. Comparative analysis shows the prefetch controller also tends to have higher prefetch accuracy and coverage than pure hardware or software techniques. ii ACKNOWLEDGMENTS I feel fortunate to have so many people to thank for helping me reach this point in my career. I am indebted to my academic advisor, David Lilja, for providing me with a great deal of freedom in choosing the direction of my research and for being exceptionally generous with his time. Professors Pen Yew, Matthew O'Keefe and Vipin Kumar have offered useful insights into this work. Matthew O'Keefe and his research group have provided numerous resources to aid in the development and use of my simulation environment. provided invaluable help in adapting their simulation tools for this research. Corey Plender also was instrumental in expanding the capabilities of these tools. Thanks to Aaron Sawdey for sharing …